1. Field of the Invention
This invention relates to a multi-layered wiring structure of a semiconductor integrated circuit device, and more particularly to a multi-layered structure preferably used for a device having three or more wiring layers formed therein.
2. Description of the Related Art
In recent years, it has been required to provide the multi-layered structure in large scale integrated circuits as the circuit construction thereof becomes more complicated to attain the high integration density and highly sophisticated functions. Conventionally, with the multi-layered wiring structure, the design margins of via holes formed in an interlaid insulation film between wiring layers and the pattern of the wiring layers are set to a preset value, for example, 0.60 .mu.m. For this reason, abnormal etching may tend to easily occur in the process of patterning the upper layer formed at a higher level because of the presence of stepped portions caused by formation of the lower wiring layer, via holes or the like. For example, in the process of patterning the upper wiring layer, the lower wiring layer lying below the upper wiring layer may be sometimes etched. If such abnormal etching occurs, an increase in the wiring resistance, wiring breakage, electromigration or the like may occur so that the circuit function may be lowered and an operation error may occur, thereby lowering the manufacturing yield and degrading the reliability.
Further, since no special attention is generally paid to the positions of stepped portions of the upper and lower wiring layers in the designing process for the multi-layered wiring structure, the stepped portions of the upper and lower wiring layers may overlap each other. If the stepped portions of the wiring layers overlap each other, the planarization effected by formation of the interlaid insulation film cannot be satisfactorily attained on the overlapped portion and a large stepped portion will be formed in the interlaid insulation film. It is confirmed that the stepped portion caused in the interlaid insulation film becomes larger with an increase in the number of the laminated wiring layers. As a result, the film thickness of a photoresist in the large stepped portion becomes larger and it becomes necessary to increase the amount of exposure with respect to that portion of the interlaid insulation film in which the large stepped portion has been formed when the photolithographic step is effected to form via holes or pattern the wiring layers. Generally, the apparent thickness of the to-be-etched material on the stepped portion is large and the apparent film thickness of the material increases when the stepped portion becomes larger, and therefore, it becomes necessary to increase the etching amount. As a result, the pattern conversion error for the pattern (wiring layer, via holes and the like) of the upper layer formed at a higher level will become larger. In addition, when an over-etching amount increases, the mark for mask alignment and the surface of the field oxide film around the mark become rough and as a result the misalignment and variation in the mask alignment become large. This is because the surface of the plasma SiO film or Si which is the underground of the mask alignment mark which is formed of Al-Si, Al-Si-Cu or the like on the dicing line will be made rough by chlorine-series radicals or the like used in the RIE method, thus making it difficult to effect the precise mask alignment.
Thus, with the conventional multi-layered wiring structure, abnormal etching tends to be more easily caused in the upper wiring layer formed at a higher level by the presence of the stepped portion formed by formation of the lower wiring layer and via holes, and the abnormal etching causes various problems as described above.